The artificial intelligence buildout of 2024 through 2026 has concentrated an extraordinary amount of global economic value creation into a supply chain that terminates, at its most critical point, in a relatively small number of fabrication facilities on the island of Taiwan. Nvidia’s H100 and H200 GPUs — the primary training and inference substrate for frontier AI models — are manufactured exclusively by TSMC. So are AMD’s competing AI accelerators, Apple’s M-series chips, and the custom AI silicon that AWS, Google, and Microsoft have each developed as alternatives to Nvidia’s architecture. TSMC manufactures the overwhelming majority of the world’s most advanced semiconductors, and its leading-edge facilities are concentrated in Hsinchu and Tainan, within range of Chinese military assets in a geopolitically contested strait.
The technology industry has known about this concentration risk for years. The pandemic-era chip shortage of 2021 to 2022 made it visible to the broader economy and policy community. The AI buildout has made it an acute strategic vulnerability. Understanding the actual state of semiconductor supply chain diversification efforts — what has been invested, what has been built, what the realistic timeline is, and where the bottlenecks that no one is talking about actually sit — requires a more honest accounting than either the geopolitical alarm or the reassuring policy narrative typically provides.
TSMC’s Actual Monopoly Position
TSMC’s dominance at leading-edge semiconductor nodes is not a quirk of market competition — it is the product of decades of compounding investment in process technology, equipment relationships, and process engineering talent that no competitor has been able to replicate. At 3 nanometre and 2 nanometre nodes — where the most computationally demanding AI chips are manufactured — TSMC is effectively the only volume manufacturer in the world. Samsung has some 3nm capacity but has struggled with yield rates that limit its ability to capture high-value AI chip production. Intel is targeting competitive leading-edge production but has not yet achieved it at scale.
The technical barriers to replicating TSMC’s leading-edge process are not simply a matter of capital expenditure. The process recipes — the precise sequence of deposition, etching, doping, and measurement steps that define a working node — are the product of continuous refinement across billions of wafers and thousands of engineers who have spent careers optimising specific manufacturing processes. The equipment relationships with ASML (which makes the extreme ultraviolet lithography machines that leading-edge fabrication requires and is itself a near-monopoly supplier) and with materials suppliers add further layers of concentrated dependency.
Nvidia’s relationship with TSMC is the most visible expression of this dependency. The AI compute demand that Nvidia is capturing is entirely contingent on TSMC’s ability to produce the chips that Nvidia designs. When Nvidia announces a new GPU architecture, the production ramp is determined by TSMC’s capacity allocation decisions as much as by Nvidia’s own manufacturing plans. This is a supply chain structure where the designer has the brand recognition and the margin, but the manufacturer holds the physical production chokepoint.
The Advanced Packaging Bottleneck Nobody Talks About
Semiconductor supply chain discussions focus heavily on fabrication — the front-end process of building transistors on silicon wafers — but the current AI chip generation has created an equally acute bottleneck in advanced packaging that receives much less attention. Modern AI accelerators, including Nvidia’s H-series GPUs, combine multiple chips into a single package using CoWoS (Chip-on-Wafer-on-Substrate) and similar advanced packaging technologies that allow different chips to communicate at high bandwidth while being physically adjacent rather than connected through PCB traces.
This advanced packaging capability is also primarily concentrated at TSMC. TSMC’s CoWoS capacity has been a limiting factor in Nvidia GPU production — in 2023 and early 2024, TSMC’s CoWoS capacity was fully allocated and constrained the number of H100s that could ship, independently of wafer production capacity. The packaging bottleneck is less discussed than the fabrication dependency but represents an equivalent supply chain chokepoint at the current state of AI chip architecture.
Advanced packaging diversification is harder to accelerate than wafer fabrication for a specific reason: the process is tightly coupled to the chip design. A new advanced packaging supplier must learn the specific bonding, alignment, and testing requirements of each chip design, which takes time and yield learning that cannot be shortcut by capital expenditure alone. Cloud providers building custom AI silicon — AWS’s Trainium, Google’s TPUs — have some flexibility in their packaging architectures, but they too depend on leading-edge packaging capacity that is geographically concentrated.
The CHIPs Act: What It Has and Has Not Accomplished
The US CHIPs and Science Act, signed into law in 2022 with $52 billion in semiconductor manufacturing subsidies and research funding, represented the most significant US industrial policy investment in decades. The headline achievements by 2026 are real: TSMC’s Arizona fab in Phoenix is producing chips at N4 (4 nanometre equivalent) process with plans to expand to N2; Intel’s Ohio facility is under construction; Samsung’s Taylor, Texas fab is progressing. These are genuine additions to US semiconductor manufacturing capacity that did not exist before the CHIPs Act incentives.
The honest accounting of what the CHIPs Act has accomplished, however, requires several qualifications. The fabs that are operational or under construction in the US are one to two generations behind the leading-edge production that remains concentrated in Taiwan. TSMC’s Arizona facility producing N4 is meaningful capacity, but TSMC’s Taiwan facilities are producing N2 and preparing N1.4; the frontier has moved while the US investments were being built. A supply chain disruption that affected TSMC’s most advanced facilities would affect production that the US CHIPs Act facilities cannot replicate in 2026.
The workforce challenge has also been more significant than proponents anticipated. Semiconductor manufacturing requires highly specialised process engineers who have experience with specific equipment and process flows; the US workforce with these skills is limited, and TSMC has had to import engineers from Taiwan for its Arizona facility at significant cost and logistical complexity. Building the talent pipeline for a world-class semiconductor manufacturing ecosystem takes a generation of educational and training investment that a three-year subsidy program cannot compress.
What the Technology Companies Are Actually Doing About It
The largest technology companies that depend on TSMC’s production are pursuing several strategies to reduce concentration risk, with varying degrees of success. Custom silicon development — designing proprietary AI accelerators optimised for specific workloads — reduces dependence on Nvidia’s architecture and creates some optionality in manufacturing partners, since custom designs can in principle be manufactured by any leading-edge foundry. Apple’s in-house chip design capability is the most mature example of this strategy, though Apple remains entirely dependent on TSMC for manufacturing.
Chiplet architectures — modularising chip design into multiple smaller dies that can be combined in packaging rather than designing monolithic chips — reduce the leading-edge wafer area required per chip and create more flexibility in sourcing. A chiplet design that puts the compute-intensive cores on leading-edge TSMC wafers but uses more commoditised nodes for I/O and memory interfaces can partially reduce the leading-edge concentration risk. AMD and Intel have pursued this architecture aggressively; Nvidia has been more conservative given the performance advantages of monolithic GPU dies for specific workloads.
Geographic diversification of TSMC’s own capacity is the most direct solution but proceeds at TSMC’s pace and at TSMC’s capital requirements. TSMC is building in Japan (Kumamoto), in Germany (Dresden), and in the US (Phoenix) — three geographically dispersed additional sites. These sites collectively add meaningful capacity outside Taiwan but remain at process nodes behind TSMC’s most advanced Taiwan production. The full diversification of leading-edge production — if it ever happens — is a 2030 to 2035 timeline, not a 2026 reality.
The Geopolitical Risk That Cannot Be Hedged Quickly
The Taiwan strait tension that underpins the semiconductor supply chain fragility discussion has not resolved in any direction since it became a prominent geopolitical concern in 2022. The status quo of managed deterrence continues, with the US maintaining security commitments to Taiwan while China maintains its claim to sovereignty and its military posture in the strait. This equilibrium has held and may continue to hold — the economic disruption of a military conflict would be catastrophic for all parties — but it is not a supply chain risk that can be hedged through normal portfolio management or strategic inventory holding.
The semiconductor industry’s response to this risk — the CHIPs Act investments, TSMC’s geographic diversification, the custom silicon programmes — represents the structural hedging that is actually feasible over a decade-long timeframe. In the near term, the AI compute buildout is proceeding on a supply chain foundation that would be severely disrupted by a Taiwan strait conflict in ways that no amount of quarterly earnings guidance or capital expenditure announcement can change. That risk is priced into geopolitical risk assessments and strategic planning but cannot be eliminated through any commercially available mechanism.
For investors and enterprises that depend on AI compute: the semiconductor supply chain fragility is a tail risk, not a base case, and operational planning should reflect that calibration. The more actionable near-term consideration is that TSMC’s capacity allocation decisions will continue to determine the supply of leading-edge AI chips, and that demand from hyperscalers, Nvidia’s orders, and Apple’s product roadmap will compete for that allocation in ways that create periodic supply constraints. Managing that constraint — through strategic inventory, long-term supply agreements, and the custom silicon diversification that reduces Nvidia dependency — is the practical risk management available to large technology consumers today.
